PCIe Lanes

PCIe lanes are the individual data links in a PCI Express (Peripheral Component Interconnect Express) slot that connect a GPU, SSD, or network card to the CPU chipset. Each lane is a serial point-to-point connection that can transfer data in both directions simultaneously. Common configurations: x16 (16 lanes, standard for GPUs), x8, and x4. PCIe Gen4 provides ~2 GB/s per lane (32 GB/s for x16), and Gen5 doubles that to ~4 GB/s per lane (64 GB/s for x16). In multi-GPU servers, each GPU gets a certain number of lanes; if all x16 slots are populated, the CPU's total lane count (often 48 or 80 on AMD/Xeon) is split, leading to x8 or even x4 per GPU. Fewer lanes reduce bandwidth for inter-GPU communication via NVLink or for CPU-to-GPU transfers. For LLM inference and training, PCIe bandwidth matters for initial model loading, data sharding, and checkpoint saving. However, during intensive compute, GPUs rarely saturate PCIe because they primarily work from HBM. But in cases where model shards must be swapped in/out of HBM (e.g., offloading to system RAM), slow PCIe becomes a bottleneck. For AI builders, ensure each GPU has at least x16 PCIe Gen4 lanes for production servers, and prefer NVLink for inter-GPU communication to avoid PCIe congestion. PCIe topology also affects latency for gradient sync during training-using NVLink reduces reliance on PCIe. Tools like nvidia-smi report PCIe link speed and width. When building custom hardware, check CPU and chipset lane allocations to avoid oversubscribing.